Title :
A 3D integration testing vehicle with TSV interconnects
Author :
Tiwei Wei ; Qian Wang ; Ziyu Liu ; Yinan Li ; Dejun Wang ; Tao Wang ; Jian Cai
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Abstract :
3D integration is one of the potential solutions for extending Moore´s momentum in the next decennium. Through silicon via (TSV) is a key interconnect technology for future´s higher performance and system integration with vertical stacked chips in package, which can achieve smaller interconnection delay, heterogeneous technologies integration and potentially lower cost and reduce time-to-market. In this paper, a testing vehicle of 3D stacking dies with TSVs as the major interconnect was designed. A dummy die with 5 μm diameter TSVs was fabricated and assembled on a silicon interposer, which has TSVs as well. The dummy die/chip was bonded on the interposer through Cu-Sn-Cu bonding at 280°C, and then, the bonded module was assembled on designed testing board.
Keywords :
copper alloys; integrated circuit bonding; integrated circuit design; integrated circuit interconnections; integrated circuit packaging; integrated circuit testing; three-dimensional integrated circuits; tin alloys; 3D integration testing vehicle; 3D stacking dies; Cu-Sn-Cu; Moore momentum; TSV interconnect technology; bonded module; designed testing board; dummy die; heterogeneous technology integration; interconnection delay; silicon interposer; size 5 mum; temperature 280 degC; through silicon via; vertical stacked chips;
Conference_Titel :
Electronic Materials and Packaging (EMAP), 2012 14th International Conference on
Conference_Location :
Lantau Island
Print_ISBN :
978-1-4673-4945-1
Electronic_ISBN :
978-1-4673-4943-7
DOI :
10.1109/EMAP.2012.6507850