DocumentCode
2042167
Title
Interconnection network behavior on a multicomputer in the parallelization of the MPEG coding algorithm. Worm-hole vs. packet-switching routing
Author
Olivares, T. ; Cuenca, P. ; Quiles, F.J. ; Garrido, A. ; Sanchez, J.L. ; Duato, J.
Author_Institution
Dept. of Inf., Castilla-La Mancha, Albacete, Spain
fYear
1997
fDate
18-21 Dec 1997
Firstpage
48
Lastpage
53
Abstract
We propose the implementation of a MPEG encoder developed by the University of California at Berkeley on a multicomputer system. Since this application is in real time, we present a mapping of the video sequence between the EPs of the architecture, where the communication between EPs is minimized. We also propose the necessary load/store process with a simple mechanism input/output, where the global distribution process latency is compensated. Idonety of the topology of the system is analyzed, together with the most adequate commutation technique for the interconnection network. Finally the incidence of the frame format on the system communication performance is analyzed
Keywords
data compression; multiprocessing systems; multiprocessor interconnection networks; packet switching; parallel algorithms; real-time systems; video coding; MPEG coding algorithm; MPEG encoder; commutation technique; frame format; global distribution process latency; interconnection network behavior; load/store process; multicomputer system; packet switching routing; parallelization; simple mechanism input/output; system communication performance; system topology; video sequence; Compression algorithms; Delay; HDTV; Intelligent networks; Multiprocessor interconnection networks; Parallel processing; Transform coding; Video compression; Video on demand; Video sequences;
fLanguage
English
Publisher
ieee
Conference_Titel
High-Performance Computing, 1997. Proceedings. Fourth International Conference on
Conference_Location
Bangalore
Print_ISBN
0-8186-8067-9
Type
conf
DOI
10.1109/HIPC.1997.634469
Filename
634469
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