Title :
The application specific instruction processor for AES
Author :
Chen, Renhai ; Jia, Zhiping ; Li, Yibin ; Xia, Hui ; Li, Xin
Author_Institution :
Comput. Sci. & Technol. Dept., Shandong Univ., Jinan, China
Abstract :
In order to raise the efficiency of execution, the hardware realization of AES has been hot research area for decade. The development of compact architectures for AES, optimized for the minimum area, is essential for the embedded device as well as the emerging sensor network implementation. A processor optimized for AES is proposed in this paper. An ESL design flow is used in this development. Four dedicated instructions are proposed and implemented on the standard FPGA platform. In this paper, the development of dedicated processor is described, which is based on the ESL (Electronic System Level) methodology. Several dedicated instructions are proposed and implemented to the FPGA platform. Compared to ARM ISA, our processor can achieve 46.5% performance improvement with much less memory requirement.
Keywords :
cryptography; field programmable gate arrays; wireless sensor networks; ARM ISA; ESL design flow; advanced encryption standard; application specific instruction processor; electronic system level methodology; embedded device; sensor network implementation; standard FPGA platform; Assembly; Computer architecture; Encryption; Europe; Field programmable gate arrays; Hardware; Registers; AES; ASIP; ESL; FPGA;
Conference_Titel :
Electronics Computer Technology (ICECT), 2011 3rd International Conference on
Conference_Location :
Kanyakumari
Print_ISBN :
978-1-4244-8678-6
Electronic_ISBN :
978-1-4244-8679-3
DOI :
10.1109/ICECTECH.2011.5941928
