A circuit extractor based on a novel method to represent layout regions

This paper presents a circuit extractor based on a novel method to represent layout regions comprising maximally-horizontal layout regions termed X-spans and on nonoverlapping vertical regions termed Y-spans. The paper also discusses the characteristics required by the extractor structure to properly support the required tasks such as the numeration of nodes and the extraction of transistors. Most of the primitive operations which are necessary to support a circuit extractor based on a layout representation using X and Y spans are presented and special attention is paid to the solution of the the difficult problem of consolidating node numbers