A Low Power Dynamic Reconfigurable Processor using Logarithmic Number System for Software Radio Equalizers

This paper presents the design of a dynamic reconfigurable processor using an array of two dimensional logarithmic numbering system (LNS) processing elements and registers. By programming the processor, the array configures dynamically during operation and executes the required task with different structures in each phase. The proposed coarse grain array architecture is suitable for implementation of software radio baseband equalizers. Since redundant elements found in fine grained structures are reduced, the design consumes less chip area and power. Several different equalizer algorithms including the CMA for QPSK and BPSK signals, the finite interval CMA and the sliding window CMA equalizers are implemented and programmed on the proposed processor array and successive operation is shown. The architecture is designed in a 0.13 ¿m CMOS technology and simulated for extraction of chip specifications. Power consumption, operation speed, gate count and chip area of the design are reported.