A new architecture for the generation of picture based CAPTCHA: A level constrained CSE low power synthesis methodology for fixed point FIR filters

The problem of designing FIR filters has received a great attention during the last decade, as the filters are suffering from a large number of multiplications, leading to excessive area and power consumption even if implemented in full custom integrated circuits. Early works have focused on replacing multiplications by decomposing them into simple operations such as addition, subtraction and shifting. As the coefficients of an application specific filter are constant, the decomposition is more efficient than employing multipliers. For complexity mitigation all coefficients of a transposed-form FIR filter are considered as a whole and replaced by a single multiplier block. This is been done using the CSD based technique. The redundancy across the coefficients in the multiplier block is then exploited to share computations and reduce the number of adders. To effectively enable such sharing, a variety of methods have been developed. In this paper a CSE based low power synthesis methodology has been analyzed for the purpose of better power reduction compared to the previous methods.