Implementation of power-delay product reduction techniques for ultra-low-power sub-threshold SCL circuits

In this paper, we have primarily focused on the implementation of techniques to reduce power-delay product of sub-threshold source coupled logic (STSCL) circuits. Here the comparisons have been drawn to derive the performance of STSCL, STSCL-SFB (sub-threshold source coupled logic circuits with source follower buffer at output stage) and STSCL-PUSHPULL (sub-threshold source coupled logic circuits with push-pull amplifier at output stage) circuits in terms of PDP. The power dissipation has been kept same and the delay has been compared for all the circuits. Further, the analytical results measured in 180-nm CMOS technology showed an improvement of delay by a factor of 3 times. All the circuits have been designed in Cadence VIRTUOSO environment for simulation purpose.