CAD tools for variation tolerance

Process variability greatly affects power and timing of nanometer scale CMOS circuits, leading to parametric yield loss due to both timing and power constraint violations. This parametric yield loss will continue to worsen in future technologies as a result of increasing process variations (Nassif, 2000) and the increased importance of leakage power. Hence, statistical techniques are required to maximize parametric yield under given power and frequency constraints. Recently, much progress has been reported in the area of statistical modeling of leakage power (Rao et al., 2004) and circuit timing. These techniques are useful in analyzing the impact of process variations on performance and power in nanometer CMOS designs. In this extended abstract, we outline the need for statistical optimization methods.