• DocumentCode
    2050159
  • Title

    Adaptive Low Power RTPG for BIST based test applications

  • Author

    John, R.T. ; Sreekanth, K.D. ; Sivanantham, S.

  • Author_Institution
    Sch. of Electron. Eng., VIT Univ., Vellore, India
  • fYear
    2013
  • fDate
    21-22 Feb. 2013
  • Firstpage
    933
  • Lastpage
    936
  • Abstract
    Power reduction during testing is an important concern in scan based tests. But methods to reduce shift power will results in test coverage loss. So a Low Power Random Test Pattern Generator (LPRTPG) is presenting to improve the tradeoff between shift power reduction and the test coverage loss. To get the required tradeoff, an adaptive type technique is utilizing where the previous test responses are given as feedback to a transition controller which is capable of generating highly correlated test patterns. The experimental results on ISCAS´89 benchmark circuits´ shows efficiency of the work in terms of reduction in test power.
  • Keywords
    built-in self test; power aware computing; BIST based test applications; adaptive low power RTPG; adaptive type technique; low power random test pattern generator; power reduction; scan based tests; shift power reduction; test coverage loss; Benchmark testing; Built-in self-test; Circuit faults; Logic gates; Switches; Vectors; VLSI Testing; built-in self test; low power; test patterns; transition controller;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Information Communication and Embedded Systems (ICICES), 2013 International Conference on
  • Conference_Location
    Chennai
  • Print_ISBN
    978-1-4673-5786-9
  • Type

    conf

  • DOI
    10.1109/ICICES.2013.6508185
  • Filename
    6508185