Gradient method based design methodology for time and area optimization of a pipelined attached processor architecture

A procedure for producing a design of a pipelined attached processor is described. It assumes that a set of algorithms and their frequencies of execution are specified. Then it determines designs that tend to minimize the execution time-cost product and execution time²-cost product, using gradient methods involving steepest descent. The designs are produced by allocating hardware subsystems such as memory subsystems, processors and routers subject to user resource constraints. The processors are assumed to be constructed of dynamic memory-to-memory pipelines