Framework for dynamic estimation of power-supply noise and path delay

Supply noise is a contributing factor for yield loss that has to be taken into account when designing fault tolerant systems. Extensive logic switching in today´s circuits cause this supply noise that results in increase in path delays that can fail design specifications. Accurate estimation of dynamic supply noise is essential to reduce false failures detected in test mode caused by over-stressed grid. Current research has not thoroughly addressed practical methods for simulating dynamic power supply currents across an IC. We present a convolution-based dynamic method to estimate both IR and Ldi/dt drop and also predict the increase in path delays caused by supply noise. However, it is infeasible to account for increase in path delay for all ATPG test patterns by carrying out full-chip SPICE simulations. We address this issue by using a technique that uses simulations of individual extracted paths. We also present a divide-and-conquer strategy to estimate power-supply noise and delays that can be leveraged to larger designs. Simulation results for the C6288 ISCAS´85 benchmark circuits are presented.