Title :
BIST for logic and local interconnect resources in a novel mesh of cluster FPGA
Author :
Rehman, Saeed-ur ; Benabdenbi, Mounir ; Anghel, Lorena
Author_Institution :
TIMA Lab., UJF, Grenoble, France
Abstract :
This paper presents new Built-In Self-Test (BIST) schemes for fault detection and diagnosis of Basic Logic Element (BLE) and intra-cluster (local) interconnect of a novel mesh of cluster FPGA. The proposed schemes avoid redundant test/diagnosis configurations by merging multiple configurations without losing diagnostic resolution. Efficiency of these schemes is calculated in terms of respective number of test/diagnosis configurations for the new FPGA. Results show that 50 BIST configurations are required for a complete test and diagnosis of the cluster. The testability aspects of this FPGA are explored in comparison with the classic clustered-mesh FPGA of the same parameters.
Keywords :
built-in self test; fault diagnosis; field programmable gate arrays; integrated circuit interconnections; logic testing; BIST; basic logic element; built-in self-test schemes; cluster FPGA; fault detection; local interconnect resources; mesh; multiple configurations; testability aspects; Built-in self-test; Clustering algorithms; Field programmable gate arrays; Multiplexing; Routing; Table lookup; BIST; SRAM-based; diagnosis; interconnect; intra-cluster; mesh of cluster; novel FPGA; test;
Conference_Titel :
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2013 IEEE International Symposium on
Conference_Location :
New York City, NY
Print_ISBN :
978-1-4799-1583-5
DOI :
10.1109/DFT.2013.6653622
