Low power and memory efficient FFT architecture using modified CORDIC algorithm

This paper presents a pipelined, reduced memory and low power CORDIC-based architecture for fast Fourier transform implementation. The proposed algorithm utilizes a new addressing scheme and the associated angle generator logic in order to remove any ROM usage for storing twiddle factors. CORDIC is implemented by a simple hardware through repeated shift-add operations Low power is achieved by the using the Coordinate Rotation Digital Computer algorithm in the place of conventional multiplication and furthermore, dynamic power consumption is reduced with no delay penalties.