Title :
On combining design for testability techniques
Author :
Parikh, Rashant S. ; Abramovici, Miron
Author_Institution :
AT&T Bell Labs., Naperville, IL, USA
Abstract :
In this paper, we present a testability-based method to combine three different DFT techniques: partial reset, partial observation, and partial scan. This approach combines the complementary strengths of the DFT techniques taking advantage of their different cost/benefit trade-offs, and results in more testable circuits with reduced design penalty
Keywords :
automatic testing; delays; design for testability; integrated circuit testing; logic testing; sequential circuits; DFT; cost/benefit trade-offs; design for testability techniques; design penalty; partial observation; partial reset; partial scan.; testable circuits; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Costs; Delay; Design for testability; Observability; Sequential analysis; Sequential circuits;
Conference_Titel :
Test Conference, 1995. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2992-9
DOI :
10.1109/TEST.1995.529868
