Realistic faults mapping scheme for the fault simulation of integrated analogue CMOS circuits

A new fault modelling scheme for integrated analogue CMOS circuits referred to as Local Layout Realistic Fault Mapping is introduced. It is aimed at realistic fault assumptions prior to the final layout by investigating typical “local” layout structures of analogue designs. Specific defects are assumed and their electrical failure modes are evaluated and mapped onto appropriate model faults. It is shown that some assumed hard faults at the schematic level are unrealistic and unlikely and that new types of fault constellations emerge including multiple or complex faults. Beside the different distribution of faults the overall number of faults decreases whereof additional realistic soft faults emerge. For an operational CMOS amplifier the overall number of 47 single hard faults assumed at schematic level dropped to 27 realistic and likely hard faults