Implementation of Static and Semi-Static Versions of a 24+8Ã\x978 Quad-Rail NULL Convention Multiply and Accumulate Unit

Author

Mallepalli, S.R. ; Kakarla, S. ; Burugapalli, S. ; Beerla, S. ; Kotla, S. ; Sunkara, P. ; Al-Assadi, W.K. ; Smith, S.C.

Author_Institution

Missouri-Rolla Univ., Rolla

fYear

2007

fDate

20-22 April 2007

Firstpage

53

Lastpage

58

Abstract

This paper focuses on implementing an unsigned 24+8x8 quad-rail (i.e., accumulator consists of 12 quad-rail signals, while the multiplier and multiplicand are each 4 quad-rail signals) multiply and accumulate (MAC) unit using the asynchronous NULL convention logic (NCL) paradigm. The design utilizes the array-structured algorithm for partial product summation, and is implemented and simulated in VHDL, the transistor level, and the physical level, using a 1.8 V 0.18 mum TSMC CMOS process. The MAC is realized using both static and semi-static versions of the NCL gates; and these two implementations are compared in terms of area, power, and speed.

Keywords

CMOS logic circuits; asynchronous circuits; hardware description languages; integrated circuit design; logic design; logic gates; multiplying circuits; NCL gates; TSMC CMOS process; VHDL simulation; array-structured algorithm; multiply and accumulate unit; partial product summation; quad-rail asynchronous null convention logic; semistatic version; size 0.18 mum; voltage 1.8 V; Algorithm design and analysis; Boolean functions; CMOS logic circuits; CMOS process; Clocks; Delay; Logic circuits; Logic design; Rails; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Region 5 Technical Conference, 2007 IEEE

Conference_Location

Fayetteville, AR

Print_ISBN

978-1-4244-1279-2

Electronic_ISBN

978-1-4244-1280-8

Type

conf

DOI

10.1109/TPSD.2007.4380351

Filename

4380351