Title :
4.8 A 28nm x86 APU optimized for power and area efficiency
Author :
Wilcox, Kathryn ; Akeson, David ; Fair, Harry R. ; Farrell, Jim ; Johnson, Dave ; Krishnan, Guhan ; Mclntyre, Hugh ; McLellan, Edward ; Naffziger, Samuel ; Schreiber, Russell ; Sundaram, Sriram ; White, Jonathan
Author_Institution :
AMD, Boxborough, MA, USA
Abstract :
Carrizo (CZ, Fig. 4.8.7) is AMD´s next-generation mobile performance accelerated processing unit (APU), which includes four Excavator (XV) processor cores and eight Radeon™ graphics core next (GCN) cores, implemented in a 28nm HKMG planar dual-oxide FET technology featuring 3 Vts of thin-oxide devices and 12 layers of Cu-based metallization. This 28nm technology is a density-focused version of the 28nm technology used by Steamroller (SR) [1] featuring eight 1× metals for dense routing, one 2× and one 4× for low-RC routing and two 16x metals for power distribution.
Keywords :
field effect transistors; metallisation; microprocessor chips; APU; Excavator processor cores; GCN cores; HKMG planar dual-oxide FET technology; Radeon graphics core next cores; accelerated processing unit; area efficiency; metallization; next-generation mobile performance; power distribution; power efficiency; Delays; Graphics; Logic gates; Multimedia communication; Streaming media; Temperature measurement;
Conference_Titel :
Solid- State Circuits Conference - (ISSCC), 2015 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4799-6223-5
DOI :
10.1109/ISSCC.2015.7062937
