DocumentCode :
2062518
Title :
9.4 A 28nm CMOS digital fractional-N PLL with −245.5dB FOM and a frequency tripler for 802.11abgn/ac radio
Author :
Xiang Gao ; Tee, Luns ; Wanghua Wu ; Kun-Seok Lee ; Paramanandam, Arvind Anumula ; Jha, Anuranjan ; Liu, Norman ; Chan, Edwin ; Li Lin
Author_Institution :
Marvell, Santa Clara, CA, USA
fYear :
2015
fDate :
22-26 Feb. 2015
Firstpage :
1
Lastpage :
3
Abstract :
The fast adaptation of WiFi 802.11ac 256-QAM mode requires RF clocks with very low integrated phase error to deliver good EVM performance. On the other hand, smaller area and lower power are always desired for lower cost and longer battery life. This work presents a 28nm CMOS LO design for dual-band 802.11abgn/ac radio with overall architecture shown in Fig. 9.4.1. It addresses the aforementioned challenges with a low-noise integrated XTAL oscillator, a fractional-N digital PLL utilizing 1) background reference clock-doubler duty-cycle error correction and quantization noise cancellation, 2) non-periodic DCO dithering and compensation, and an offset LO frequency plan based on a self-mixing frequency tripler. The PLL design achieves 0.36° integrated phase error or 0.17ps rms jitter while consuming 9.5mW, leading to a record FOM of -245.5dBforfrac-N PLLs.
Keywords :
CMOS digital integrated circuits; digital phase locked loops; error correction; frequency multipliers; jitter; quadrature amplitude modulation; radiofrequency oscillators; wireless LAN; CMOS LO design; CMOS digital fractional-N PLL design; EVM performance; FOM; RF clocks; Wi-Fi 802.11ac 256-QAM mode; background reference clock-doubler duty-cycle error correction; battery life; dualband 802.11abgn-ac radio; frequency tripler; jitter; low-noise integrated XTAL oscillator; nonperiodic DCO compensation; nonperiodic DCO dithering; offset LO frequency plan; phase locked loops; power 9.5 mW; quantization noise cancellation; self-mixing frequency tripler; size 28 nm; very low integrated phase error; CMOS integrated circuits; Clocks; Jitter; Noise; Oscillators; Phase locked loops; Quantization (signal);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid- State Circuits Conference - (ISSCC), 2015 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4799-6223-5
Type :
conf
DOI :
10.1109/ISSCC.2015.7062978
Filename :
7062978
Link To Document :
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