Symbolic verification of CMOS synchronous circuits using characteristic functions

Author

Kukimoto, Yuji ; Fujita, Masahiro ; Tanaka, Hidehiko

Author_Institution

Dept. of Electr. Eng., Tokyo Univ., Japan

fYear

1991

fDate

12-15 May 1991

Abstract

The authors present a functional verification method for CMOS synchronous circuits by representing circuit behaviors with characteristic functions. Bidirectional signal effects and charge effects are formalized based on these functions. This method makes it possible to verify dynamic switch-level circuits, such as pass-transistor networks and precharge logic circuits, which cannot be accurately modeled at gate-level. An automatic switch-level verification system has been implemented, and experimental results are reported

Keywords

CMOS integrated circuits; integrated logic circuits; logic design; sequential circuits; CMOS synchronous circuits; automatic switch-level verification system; characteristic functions; charge effects; circuit behaviors; dynamic switch-level circuits; functional verification method; pass-transistor networks; precharge logic circuits; symbolic verification; Circuit simulation; Hardware; Integrated circuit modeling; Laboratories; Logic circuits; Semiconductor device modeling; Switches; Switching circuits; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0015-7

Type

conf

DOI

10.1109/CICC.1991.164009

Filename

164009