DocumentCode :
2063462
Title :
A survey on power-delay reduction techniques for ultra-low-power subthreshold SCL circuits
Author :
Vyas, Sumit ; Rai, Sanjeev
Author_Institution :
Dept. of Electron. & Commun. Eng., Motilal Nehru Nat. Inst. of Technol., Allahabad, India
fYear :
2012
fDate :
16-18 March 2012
Firstpage :
1
Lastpage :
5
Abstract :
In this paper, we have primarily focused on the survey of power-delay performance of sub-threshold source coupled logic (STSCL) and STSCL-SFB (sub-threshold source coupled logic circuits with a source-follower buffer stage at output of each SCL gates) circuits. Here the comparisons have been drawn to derive the performance of STSCL and STSCL-SFB circuits in terms of PDP. The power dissipation has been kept same and the delay has been compared for both the circuits. Further, the analytical results measured in 180-nm CMOS technology showed an improvement of delay by a factor of 3 times. All the circuits have been designed in Cadence VIRTUOSO environment for simulation purpose.
Keywords :
CMOS logic circuits; buffer circuits; coupled circuits; logic circuits; power electronics; simulation; CMOS technology; Cadence VIRTUOSO environment; STSCL-SFB; power-delay performance; power-delay reduction techniques; simulation; source-follower buffer; sub-threshold source coupled logic circuit; ultra-low-power subthreshold SCL circuits; CMOS integrated circuits; Capacitance; Delay; Logic gates; Power demand; Resistance; Topology; Source-coupled logic (SCL); subthreshold SCL (STSCL); ultralow-power circuits; weak inversion SCL (WiSCL);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Engineering and Systems (SCES), 2012 Students Conference on
Conference_Location :
Allahabad, Uttar Pradesh
Print_ISBN :
978-1-4673-0456-6
Type :
conf
DOI :
10.1109/SCES.2012.6199051
Filename :
6199051
Link To Document :
بازگشت