Design Methodology of Subthreshold Three-Stage CMOS OTAs Suitable for Ultra-Low-Power Low-Area and High Driving Capability

A design methodology for three-stage CMOS OTAs operating in the subthreshold region is presented. The procedure is focused on the development of ultra-low-power amplifiers requiring low silicon area but being able to drive high capacitive loads. Indeed, by following the presented methodology we designed a CMOS OTA in a 0.35- μm technology that occupies only 4.4·10^-3 mm², is powered with a 1-V supply, exhibits 120-dB DC gain and is able to drive a capacitive load up to 200 pF. Thanks to proposed methodology, the OTA is able to provide a 20-kHz unity gain bandwidth while consuming 195 nW, even under the high load considered. Moreover, the slew rate enhancer circuit in addition to the class AB output stage allows an average slew rate higher than 5 mV/μs with the 200 pF load. Comparison with prior art shows an improvement factor in the figures of merit higher than 5.