Incremental Fault Emulation

The fault coverage of tests for microelectronic circuits must be evaluated as part of the test generation process. Although much faster than fault simulation, fault-grading a large and complex design using fault emulation can still take up a considerable amount of time. This is especially true when considering that the whole process has to be repeated when test patterns have been modified. In this paper we propose methods to reduce the number of fault emulations for repeated fault-grading runs. We further introduce algorithms to shorten the tests after an initial complete fault-grading. The algorithms have been implemented into a modular fault emulation environment. We present results obtained on the emulation system Mercury+ by Cadence.