A 25-Gb/s 32.1-dB CMOS limiting amplifier for integrated optical receivers

Author

Zhengxiong Hou ; Yipeng Wang ; Quan Pan ; Yue, C. Patrick

Author_Institution

Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Hong Kong, China

fYear

2013

fDate

28-31 Oct. 2013

Firstpage

1

Lastpage

4

Abstract

A 65-nm CMOS limiting amplifier based on three stages of a modified Cherry-Hooper amplifier with offset cancellation is presented. The trade-off between the offset cancellation range and input-referred noise is discussed. The variations on gain and bandwidth due to PVT corners are presented. The limiting amplifier achieves 32.1 dB gain and 21.6 GHz bandwidth, with a 1-V supply and a power dissipation of 33.3 mW.

Keywords

CMOS analogue integrated circuits; integrated optoelectronics; operational amplifiers; optical fibre amplifiers; optical limiters; optical receivers; CMOS limiting amplifier; PVT corners; bandwidth 21.6 GHz; bit rate 25 Gbit/s; gain 32.1 dB; input-referred noise; integrated optical receivers; modified Cherry-Hooper amplifier; offset cancellation range; power 33.3 mW; size 65 nm; transimpedance amplifier; voltage 1 V; Bandwidth; CMOS integrated circuits; CMOS technology; Gain; Limiting; Noise; Temperature measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC (ASICON), 2013 IEEE 10th International Conference on

Conference_Location

Shenzhen

ISSN

2162-7541

Print_ISBN

978-1-4673-6415-7

Type

conf

DOI

10.1109/ASICON.2013.6811897

Filename

6811897