• DocumentCode
    2065617
  • Title

    Self-synchronous circuit designs, SSFPGA and SSRSA for low voltage autonomous control and tamper resistivity

  • Author

    Ikeda, Makoto

  • Author_Institution
    Dept. of Electr. Eng. & Inf. Syst., Univ. of Tokyo, Tokyo, Japan
  • fYear
    2013
  • fDate
    28-31 Oct. 2013
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    We have been working for asynchronous control with fine-grain pipeline circuits, namely, self-synchronous circuits. We have demonstrated self-synchronous FPGA (SS-FPGA) designs with autonomous gate-level power gating to reduce energy consumption at the energy minimum operating point. We have also demonstrated self-synchronous RSA crypt-engine (SS-RSA) to realize high throughput in nominal operating voltage and low energy in low operating voltage, without any information leakage against various tampering attacks such like SPA, DPA and HO-DPA.
  • Keywords
    field programmable gate arrays; logic design; public key cryptography; DPA; HO-DPA; SPA; SS-RSA; SSFPGA; asynchronous control; autonomous gate-level power gating; energy consumption reduction; energy minimum operating point; fine-grain pipeline circuits; low voltage autonomous control; self-synchronous FPGA designs; self-synchronous RSA crypt-engine; self-synchronous circuit designs; tamper resistivity; tampering attacks; Delays; Logic gates; Pipeline processing; Pipelines; Throughput; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC (ASICON), 2013 IEEE 10th International Conference on
  • Conference_Location
    Shenzhen
  • ISSN
    2162-7541
  • Print_ISBN
    978-1-4673-6415-7
  • Type

    conf

  • DOI
    10.1109/ASICON.2013.6811907
  • Filename
    6811907