Title :
23.3 A highly integrated smartphone SoC featuring a 2.5GHz octa-core CPU with advanced high-performance and low-power techniques
Author :
Mair, Hugh ; Gammie, Gordon ; Wang, Alice ; Gururajarao, Sumanth ; Lin, Ichiro ; HsinChen Chen ; Wuan Kuo ; Rajagopalan, Anand ; Wei-Zheng Ge ; Lagerquist, Rolf ; Rahman, Syed ; Chung, C.J. ; Wang, Simon ; Lee-Kee Wong ; Yi-Chang Zhuang ; Li, Kent ; Jidon
Author_Institution :
MediaTek, Austin, TX, USA
Abstract :
This paper describes the high-performance CPU design of a heterogeneous octa-core CPU complex, incorporated into a highly integrated mobile SoC for smartphone applications. The SoC is fabricated in a 28nm high-x metal-gate CMOS, and has a die size of 89mm2. Cu pillars are used for the die-to-substrate interface with fine substrate trace pitch. The SoC is packaged in a 14mmx14mm, 832 ball, 0.4mm pitch BGA. An integrated cellular modem supports rei. 9, cat. 4 LTE (FDD and TDD), while additional cellular and RF connectivity includes DC-HSPA+, TD-SCDMA, EDGE, 802.11ac, Bluetooth LE, multi-GNSS (GPS, GLONASS, Beidou, Galileo & QZSS), and ANT+. Multimedia features are highlighted by a high-performance Power-VR Series6 GPU, support for WQXGA displays (2560×1600), a 20Mpixel image processor and camera interface, and ultra-HD video playback support for H.264 and VP9.
Keywords :
CMOS digital integrated circuits; Long Term Evolution; ball grid arrays; high-k dielectric thin films; integrated circuit design; modems; smart phones; system-on-chip; 802.11ac; ANT; BGA; Beidou; Bluetooth LE; DC-HSPA; EDGE; FDD; GLONASS; GPS; Galileo; H.264; QZSS; RF connectivity; TD-SCDMA; TDD; VP9; WQXGA displays; advanced high-performance technique; camera interface; cat. 4 LTE; cellular connectivity; copper pillars; die size; die-to-substrate interface; frequency 2.5 GHz; heterogeneous octa-core CPU complex; high-performance CPU design; high-performance Power-VR Series6 GPU; highly-integrated mobile SoC; highly-integrated smartphone SoC; image processor; integrated cellular modem; low-power technique; metal-gate CMOS; multiGNSS; multimedia features; rei. 9; size 28 nm; substrate trace pitch; ultraHD video playback support; Clocks; Delays; High definition video; Logic gates; Silicon; Switches; System-on-chip;
Conference_Titel :
Solid- State Circuits Conference - (ISSCC), 2015 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4799-6223-5
DOI :
10.1109/ISSCC.2015.7063107
