DocumentCode
2066239
Title
Low temperature multi layer stack wafer bonding technology development
Author
Jeung, Won Kyu ; Lim, Chang Hyun ; Yi, Sung
Author_Institution
Samsung Electro-Mech. Co., Ltd., Suwon
fYear
2009
fDate
26-29 May 2009
Firstpage
20
Lastpage
24
Abstract
A new wafer bonding approach for 3-D packaging is designed fabricated and tested. We can summarize device market trend in next few words like Low cost, small form factor, integration, high performance, etc. During the last decades, 3-D wafer level packaging (3-D WLP) is highlighted as the next generation packaging method for satisfying market needs. 3-D WLP method has many advantages like low cost (wafer batch process), high performance (shorter electrical length), small form factor (3-D interconnection), low assembly cost and so on. One of the key technologies of 3-D packaging is wafer bonding. In wafer bonding field, low process temperature, high hermeticity, high reliability, multi layer stack and low process cost are main technical stream. Among various fabrication methods polymer bonding, eutectic bonding, silicon fusion bonding and anodic bonding are generally used. In case of polymer bonding, it has difficulty in high hermeticity and high reliability. In case of eutectic bonding, it has very high material cost compared to others. In case of silicon fusion bonding and anodic bonding has very high process temperature. In this paper, new anodic bonding technique is proposed for satisfying low cost, low process temperature, high hermeticity and multi layer stack. Through suggested bonding mechanism, more than 9 glasses to silicones sandwich layer is anodic ally bonded together simultaneously under 200 degree. Obviously, realized sample has very high hermeticity and bonding strength.
Keywords
glass; reliability; sandwich structures; silicones; wafer bonding; wafer level packaging; 3-D wafer level packaging; anodic bonding; bonding strength; glasses; hermeticity; low temperature wafer bonding; multi layer stack; reliability; sandwich layer; silicones; Assembly; Costs; Fabrication; Packaging; Polymers; Silicon; Temperature; Testing; Wafer bonding; Wafer scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference, 2009. ECTC 2009. 59th
Conference_Location
San Diego, CA
ISSN
0569-5503
Print_ISBN
978-1-4244-4475-5
Electronic_ISBN
0569-5503
Type
conf
DOI
10.1109/ECTC.2009.5073991
Filename
5073991
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