Software versus hardware coherence: performance versus cost

Directory-based protocols are currently the method of choice to enforce cache coherence in large-scale shared-memory multiprocessors. The problems associated with these hardware schemes include their lack of scalability, although various suggestions have been made to ameliorate this drawback, and the loss of performance due to false sharing. Software controlled cache coherence (SCCC) is an alternative that solves the scalability problem at the possible expense of a serious loss in performance since many compile-time decisions on cacheability are conservative. The authors perform a comparative study of hardware and software cache coherence based on instruction-level simulations of two benchmarks. The studies do not shy away from realistic SCCC difficulties such as multi-word lines and DOAcross loops. The simplification in hardware and in protocols result in a slight performance loss for SCCC, a loss that becomes relatively smaller and negligible with larger memory latencies.<>