DocumentCode :
2068837
Title :
Logical Core Algorithm: Improving Global Placement
Author :
Pinto, Felipe ; Cavalheiro, Lucas ; Johann, Marcelo ; Reis, Ricardo
Author_Institution :
Inst. de Inf., Univ. Fed. do Rio Grande do Sul - UFRGS, Porto Alegre, Brazil
fYear :
2010
fDate :
5-7 July 2010
Firstpage :
69
Lastpage :
73
Abstract :
This work introduces a new technique to improve the global placement, which can be applied to any regular placer. We propose an algorithm called Logical Core, based on Google PageRanka®, which distributes probability weights to every cell in the circuit netlist. Then, these weights are used to select the most important cells for the global placement. By using this information, we are able to improve global placement in terms of wirelength. The Logical Core algorithm proposes a new complexity rule to the placement graph. This complexity has a great similarity with the Rent´s Rule. The technique improves the total wirelength in all tested cases by 4.5%.
Keywords :
VLSI; probability; Google PageRanka; VLSI; circuit netlist; complexity rule; global placement; logical core algorithm; placement graph; probability weights; regular placer; wirelength; Algorithm design and analysis; Complexity theory; Controllability; Damping; Integrated circuit interconnections; Organizations; Probabilistic logic; Algorithms and Microelectronics; Complexity; Controllability; Physical Design; Placement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI (ISVLSI), 2010 IEEE Computer Society Annual Symposium on
Conference_Location :
Lixouri, Kefalonia
Print_ISBN :
978-1-4244-7321-2
Type :
conf
DOI :
10.1109/ISVLSI.2010.114
Filename :
5571807
Link To Document :
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