A study on the performance of stress induced p-channel MOSFETs with embeded Si1−xGex source/drain

In the current work, an embedded Si_1-xGe_x source/drain p-MOSFET architecture, with varying gate length, in range of 32 nm to 50 nm, has been considered for studying the impact of induced stress on its performance. The simulation has been performed using physics-based process and device simulation tool Taurus Technology Computer Aided Design (TCAD). The simulator is calibrated with available experimental data for p-MOSFET of similar dimension. The study shows that the drive current increases significantly with Ge mole fraction in the S/D regions. A significant reduction of threshold voltage with marginal change in DIBL and sub-threshold swing has also been achieved.