Voltage controlled current starved delay cell for Positron Emission Tomography specific DLL based high precision TDC implementation

This work focuses on high performance voltage controlled current starved delay cell (CSDC) design. This delay cell will be used in Delay locked loop (DLL) based high precision Time-to-digital converter (TDC) implementation for Positron Emission Tomography (PET) application. DLL generates clocks of different phases. Sampling these clocks, sub-periodic time can be accurately measured as integer multiple of bin-size (unit delay difference between successive phases). Array of Delay locked loop (ADLL) can generate bin-size even below inverter delay for any technology node. With our delay cell, an ADLL can easily produce a bin size of 71.2ps using 100 MHz clock. Our delay cell consumes maximum static power of 267 uW with peak to peak delay mismatch of 2.86 ps and 0.684 ps rms delay mismatch. Unlike other delay cell, the transfer curve of our delay cell has lower slope and monotone decreasing function of control voltage below V_TN. Dead-band in the transfer curve is inherently removed.