A high performance digital processor for implementing large artificial neural networks

A CMOS integrated circuit is described which is capable of implementing very large digital neural networks of the multilayer perceptron (MLP) form. It incorporates on-chip training using the backpropagation algorithm, and the use of pseudorandom noise allows training with coarsely quantized weight values. Dynamic range and precision of the connection weights are automatically adjusted during training, thus allowing the circuit to adapt to different network sizes and topologies. The addition of a small, pseudorandom noise element allows the weights memory to be used more efficiently for large networks. Extensive simulation using a hardware description model over a range of problems has given a high degree of confidence in the design