A high density GaAs gate array architecture

Author

Lee, Gary ; Donckels, Boyd ; Grey, Aubrey ; Deyhimy, Ira

Author_Institution

Vitesse Semicond. Corp., Camarillo, CA, USA

fYear

1991

fDate

12-15 May 1991

Abstract

A GaAs gate array family has been developed incorporating from 100000 to 350000 raw two-input NOR gates in a sea-of-gates architecture. These arrays exhibit unloaded gate delays of 50 ps and a worst-case power dissipation of 250 μW. The authors describe the gate array cells and I/O buffers that were designed with a 0.6-μm L_eff self-aligned gate GaAs MESFET process. In addition, the array architecture is described along with the test results on a 100 K gate array test chip designed to verify array performance

Keywords

III-V semiconductors; Schottky gate field effect transistors; VLSI; field effect integrated circuits; gallium arsenide; logic arrays; 0.6 micron; 250 muW; 50 ps; GaAs gate array family; I/O buffers; MESFET; VLSI; array performance; gate array architecture; gate array cells; gate delays; power dissipation; sea-of-gates; self-aligned gate; semiconductors; test chip; test results; two-input NOR gates; Aluminum; BiCMOS integrated circuits; CMOS logic circuits; Frequency; Gallium arsenide; MESFETs; Power dissipation; Power supplies; Schottky diodes; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0015-7

Type

conf

DOI

10.1109/CICC.1991.164043

Filename

164043