DocumentCode
2072979
Title
Bumpless Ball Grid Array (BBGA) package using a solder resist cavity
Author
Kwon, Yong-Min ; Kang, Joon-Suk ; Kweon, Young-Do ; Paik, Kyung-Wook
Author_Institution
Dept. of Mater. Sci. & Eng., Korea Adv. Inst. of Sci. & Technol., Daejon
fYear
2009
fDate
26-29 May 2009
Firstpage
1552
Lastpage
1556
Abstract
In this study, the package named Bumpless Ball Grid Array (BBGA) was developed. In BBGA package, chips were buried in the cavities made with solder resist materials. For BBGA package development, epoxy based photo-patternable solder resist was used as an encapsulation material because of cost effectiveness and process simplicity. This solder resist film was laminated on the Cu plate and cavities were formed by a lithography method. After the cavity formation, chips were buried in these cavities, and then dielectric layer was applied on the solder resist and the chip surface. In this package fabrication, selecting the proper dielectric materials layer was the key issue. Therefore, proper dielectric materials and process conditions for BBGA package fabrication were investigated. Five different conventional dielectric materials were selected and processilities of these dielectric materials were tested. And for enhancing the wettability of dielectric material on a solder resist film, plasma treatment was performed. Due to the selective etching of solder resist surface, surface energy of solder resist film increased. Warpage was another issue for BBGA fabrication. Because of the warpage of Cu plate, subsequent patterning was not formed on an exact position. Therefore, by applying flattening force on BBGA, mis-alignment was reduced. And the proper dielectric material conditions for reducing warpage were investigated.
Keywords
ball grid arrays; copper; dielectric materials; encapsulation; etching; resists; solders; wetting; Cu; bumpless ball grid array package; copper plate warpage; dielectric material wettability; encapsulation material; epoxy-based photo-patternable solder resist; flattening force; package fabrication; plasma treatment; resist film lamination; solder resist cavity; solder resist surface etching; Costs; Dielectric materials; Electronics packaging; Encapsulation; Fabrication; Lithography; Materials testing; Plasma applications; Resists; Surface treatment;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference, 2009. ECTC 2009. 59th
Conference_Location
San Diego, CA
ISSN
0569-5503
Print_ISBN
978-1-4244-4475-5
Electronic_ISBN
0569-5503
Type
conf
DOI
10.1109/ECTC.2009.5074219
Filename
5074219
Link To Document