• DocumentCode
    2073496
  • Title

    Evaluation of an accelerator architecture for Speckle Reducing Anisotropic Diffusion

  • Author

    Nilakantan, Siddharth ; Annangi, Srikanth ; Gulati, Nikhil ; Sangaiah, Karthik ; Hempstead, Mark

  • Author_Institution
    Drexel Univ., Philadelphia, PA, USA
  • fYear
    2011
  • fDate
    9-14 Oct. 2011
  • Firstpage
    185
  • Lastpage
    194
  • Abstract
    Increasing chip power density has brought application specific accelerator architectures to the forefront as an energy and area efficient solution. While GPGPU systems take advantage of specialized hardware to perform computationally intensive tasks faster than chip multiprocessor (CMP) systems, accelerators are hardware units that are designed to execute a specific application efficiently. Real-time ultrasound imaging applications require the removal of multiplicative noise while maintaining a steady frame-rate, and are good candidates to explore accelerator-based systems. In this paper, we propose and evaluate the architecture of an accelerator designed to improve performance of SRAD image enhancing algorithm. We compare the projected performance of the SRAD accelerator to software implementations on a multi-core CPU and a CPU+GPU system. The proposed architecture achieves higher throughput by eliminating redundant fetches from memory and by storing intermediate data locally. The speedup of the GPU is found to be 3.2× over the CPU, while the accelerator achieved a speedup of 24×. The area efficiency of the GPU and accelerator is up to 1.6× and 370× better than the CPU, respectively. In comparison with the CPU, we find that the energy consumed for operation on a single frame is found to be 1.5× lesser on the GPU and up to 580× lesser on the accelerator.
  • Keywords
    computer graphic equipment; coprocessors; diffusion; image denoising; image enhancement; multiprocessing systems; redundancy; speckle; ultrasonic imaging; CPU+GPU system; GPGPU systems; SRAD image enhancing algorithm; accelerator based system; application specific accelerator architecture; chip power density; energy consumption; intermediate data storing; multicore CPU; multiplicative noise removal; real-time ultrasound imaging application; redundant fetches; software implementation; speckle reducing anisotropic diffusion; Arrays; Clocks; Graphics processing unit; Hardware; Registers; Speckle; Accelerator; GPU; Performance; SRAD;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Compilers, Architectures and Synthesis for Embedded Systems (CASES), 2011 Proceedings of the 14th International Conference on
  • Conference_Location
    Taipei
  • Print_ISBN
    978-1-4503-0713-0
  • Type

    conf

  • Filename
    6062044