Efficient techniques for gate leakage estimation

Author

Rao, Rahul M. ; Burns, Jeffrey L. ; Devgan, Anirudh ; Brown, Richard B.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA

fYear

2003

fDate

25-27 Aug. 2003

Firstpage

100

Lastpage

103

Abstract

Gate leakage current is expected to be the dominant leakage component in future technology generations. In this paper, we propose methods for steady-state gate leakage estimation based on state characterization. An efficient technique for pattern-dependent gate leakage estimation is presented. Furthermore, we propose the use of this technique for estimating the average gate leakage of a circuit using pattern-independent probabilistic analysis. Results on a large set of benchmark ISCAS circuits show an accuracy within 5% of SPICE results with 500× to 50000× speed improvement.

Keywords

SPICE; circuit analysis computing; computational complexity; integrated circuit modelling; leakage currents; low-power electronics; parameter estimation; probability; SPICE; average circuit gate leakage; benchmark ISCAS circuits; dominant leakage component; gate leakage estimation techniques; leakage current; pattern-dependent gate leakage estimation; pattern-independent probabilistic analysis; speed improvement; state characterization; steady-state gate leakage estimation; technology generations; CMOS technology; Circuit analysis; Circuit simulation; Gate leakage; Leakage current; Pattern analysis; Power generation; SPICE; State estimation; Steady-state;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on

Print_ISBN

1-58113-682-X

Type

conf

DOI

10.1109/LPE.2003.1231843

Filename

1231843