Title :
High performance CMOS dual-port SRAM compiler
Author :
Phuong, Hai V. ; Yee, Ming D.
Author_Institution :
VLSI Technol. Inc., San Jose, CA, USA
Abstract :
A high-density, high-performance dual-port SRAM (static RAM) compiler has been developed with standard product features. The compiler can generate different SRAM configurations with a minimum of 512 bits up to a maximum of 9 kbits. The SRAM has a typical access time of 15 ns (1.5-μm ASIC (application-specific integrated circuit) process) for the largest configuration (1 K words×9 bits or 512 words×18 bits). It is scalable to a 1-μm ASIC process with a typical access time of 9 ns. The compiler takes only five min to generate a complete layout block, a transistor netlist, or a gate-level model netlist for any SRAM configuration
Keywords :
CMOS integrated circuits; application specific integrated circuits; circuit layout CAD; integrated memory circuits; random-access storage; 0.5 to 9 kbit; 1 micron; 1.5 micron; 15 ns; 18 bit; 5 min; 9 bit; 9 ns; ASIC; CMOS dual-port SRAM compiler; access time; any SRAM configuration; application-specific integrated circuit; circuit layout; complete layout block; gate-level model netlist; scalable; standard product features; static RAM; transistor netlist; Application specific integrated circuits; CMOS technology; Circuit simulation; Circuit synthesis; Integrated circuit technology; Logic; Power dissipation; Random access memory; Read-write memory; Very large scale integration;
Conference_Titel :
ASIC Seminar and Exhibit, 1989. Proceedings., Second Annual IEEE
Conference_Location :
Rochester, NY
DOI :
10.1109/ASIC.1989.123185
