Pipeline stage unification: a low-energy consumption technique for future mobile processors

Author

Shimada, Hajime ; Ando, Hideki ; Shimada, Toshio

Author_Institution

Dept. of Inf. Electron., Nagoya Univ., Japan

fYear

2003

fDate

25-27 Aug. 2003

Firstpage

326

Lastpage

329

Abstract

Recent mobile processors are required to exhibit both low-energy consumption and high performance. To satisfy these requirements, dynamic voltage scaling (DVS) is currently employed. However, its effectiveness will be limited in the future because of shrinking the variable supply voltage range. As an alternative, we previously proposed pipeline stage unification (PSU), which unifies multiple pipeline stages without reducing the supply voltage at a power-saving mode. This paper compares effectiveness of PSU to DVS in current and future process generations. Our evaluation results show PSU will reduce energy consumption by 27-34% more than DVS after about 10 years.

Keywords

computer power supplies; low-power electronics; microprocessor chips; pipeline processing; power consumption; dynamic voltage scaling; future mobile processors; future process technology; low energy consumption; low-power consumption; multiple pipeline stages; pipeline register; pipeline stage unification; Clocks; Computer architecture; Dynamic voltage scaling; Energy consumption; Frequency; Permission; Pipelines; Power engineering and energy; Threshold voltage; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on

Print_ISBN

1-58113-682-X

Type

conf

DOI

10.1109/LPE.2003.1231888

Filename

1231888