DocumentCode
2077288
Title
Verilog simulation of Xilinx designs
Author
Cummings, Clifford E.
Author_Institution
Tektronix Inc., Beaverton, OR, USA
fYear
1994
fDate
14-16 Mar 1994
Firstpage
93
Lastpage
100
Abstract
Details design flows to capture Xilinx designs and translate them into Verilog behavioral models. Part of this material focuses on back annotation of Xilinx routed timing information into a Verilog simulation. The author also describes modified design flows to take advantage of third-party FPGA design tools and mixing of Xilinx design methodologies
Keywords
digital simulation; logic CAD; logic arrays; specification languages; FPGA design tools; Verilog behavioral models; Verilog simulation; Xilinx designs; routed timing information; Atherosclerosis; Design methodology; Field programmable gate arrays; Hardware design languages; Libraries; Pins; Product development; Routing; Signal design; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Verilog HDL Conference, 1994., International
Conference_Location
Santa Clara, CA
Print_ISBN
0-8186-5655-7
Type
conf
DOI
10.1109/IVC.1994.323742
Filename
323742
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