Customizable embedded processor architectures

In this paper, we present a framework for dynamic application customization for high-performance and low-power embedded processors. The proposed architecture is capable of utilizing application information to boost the performance and lower the power consumption of the most important microarchitectural components such as instruction/data caches and the memory subsystem. We present a design framework, including CAD support infrastructure and reprogrammable hardware support, for a dynamically customizable microarchitecture. We outline the underlying algorithms for compile-time extraction of the utilized application properties and we present the architectural principles of the hardware support. Extensive experimental results confirm the efficacy of this novel embedded processor architecture.