Third-order phase-locked loops using dual loops with improved stability

The third-order PLL has an instability problem. It is known that a system of dual loops improves the instability and suppresses the steady-state error of a third-order PLL. A conventional third-order PLL using dual loops is implemented by digital equipment. Since the digital PLL cannot be used in the high frequency band in satellite communications because of limitations of the operational frequency, conventional third-order PLL using dual loops are unavailable in such an environment. In this paper, we propose a new third-order PLL using dual loops which are implemented by analog equipment. We investigate the transient response and the steady-state behavior of the proposed PLL due to the frequency ramp transition. Results show that the steady-state phase error of the proposed PLL is suppressed. Furthermore, we show that the stability of the proposed PLL is better than that of the typical third-order PLL