An ultra low power LNA with 15dB gain and 4.4db NF in 90nm CMOS process for 60 GHz phase array radio

This paper presents a 60 GHz LNA designed in a 90 nm CMOS process with 6 metals Cu thick metal, and Ft/Fmax of 100 GHz/150 GHz demonstrating best known noise figure, gain, power consumption and size compared to earlier 60-GHz LNAs reported. It features 15 dB of gain, a measured noise figure (NF) of 4.4 dB, while drawing 3 mA from a 1.3-V supply. The use of spiral inductors enables a reduction in transistor size, total power consumption, and die size. The LNA die area with/without pads is 0.32times0.44 mm²/0.14times0.27 mm² respectively. First pass success was achieved by proper methodology of closed ground environment for passive structures and proper layout. The paper compares different transistor core sizes and different circuit topologies showing that a common source (CS) topology with a 10times1 um transistor width gives the best performance over all other options.