Characterization and modeling of Asymmetric LDD MOSFET for 65nm CMOS RF Power Amplifier design

Author

Huang, Kai-Ye ; Wang, Po-Chih ; Hung, Meng-Chi ; Jean, Yuh-Sheng ; Yeh, Ta-Hsun ; Lin, Ying-Hsi

Author_Institution

Realtek Semicond. Corp., Hsin-Chu

fYear

2008

fDate

June 17 2008-April 17 2008

Firstpage

263

Lastpage

266

Abstract

This study demonstrates an RF active device based on A-LDD (asymmetric lightly doped drain) MOSFET structure which has higher drain to gate and drain to source breakdown voltage due to removing LDD and halo doped region from the drain side. It is suitable to be used in RF PA (power amplifier) design for SoC (system on chip) in advance 65 nm node and below technology. The manufacturing of A-LDD MOSFET is compatible with standard CMOS process and no extra mask required. A RF macro model of A-LDD MOSFET is proposed by combining a bias dependent series resistance sub-circuit with BSIM4 MOS model. Besides, a cascode PA composed of A-LDD device was designed and simulated. It shows better RF power performance due to the shorter channel and the larger supply voltage are allowed for A-LDD device compared with conventional one.

Keywords

CMOS analogue integrated circuits; power amplifiers; radiofrequency amplifiers; system-on-chip; CMOS RF power amplifier design; RF active device; SoC; asymmetric LDD MOSFET; asymmetric lightly doped drain structure; size 65 nm; system on chip; CMOS technology; MOSFET circuits; Manufacturing processes; Power MOSFET; Power amplifiers; Power system modeling; Radio frequency; Radiofrequency amplifiers; Semiconductor device modeling; System-on-a-chip; A-LDD (Asymmetric Lightly Doped Drain MOSFET); BSIM4; PA (Power Amplifier); SoC (System on Chip);

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits Symposium, 2008. RFIC 2008. IEEE

Conference_Location

Atlanta, GA

ISSN

1529-2517

Print_ISBN

978-1-4244-1808-4

Electronic_ISBN

1529-2517

Type

conf

DOI

10.1109/RFIC.2008.4561432

Filename

4561432