An automatic test bench generation system

Presents an automatic test bench generation system for VHDL behavioral models. The Modeler´s Assistant, an interactive CAD tool developed at Virginia Tech, gives the graphical representation of a VHDL behavioral model, called a process model graph (PMG). The process test generator (PTG) is used to generate the stimulus/response test sets for individual processes of a PMG. The hierarchical behavioral test generator (HBTG) accepts the PMG and the test sets produced by PTG as inputs, and then hierarchically constructs a test sequence for the entire model. The test sequence is converted into a test bench by the test bench generator (TBG), and it is then used for simulation of the model. Experimental results show that the test benches generated exercise the models thoroughly