A multiprocessor DSP system using PADDI-2

Author

Sutton, Roy A. ; Srini, Vason P. ; Rabaey, Jan M.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

1998

fDate

19-19 June 1998

Firstpage

62

Lastpage

65

Abstract

We have integrated an image processing system built around PADDI-2, a custom 48 node MIMD parallel DSP. The system includes image processing algorithms, a graphical SFG tool, a simulator, routing tools, compilers, hardware configuration and debugging tools, application development libraries, and software implementations for hardware verification. The system board, connected to a SPARCstation via a custom Sbus controller, contains 384 processors in 8 VLSI chips. The software environment supports a multiprocessor system under development (VGI-1). The software tools and libraries are modular, with implementation dependencies isolated in layered encapsulations.

Keywords

VLSI; digital signal processing chips; image processing; multiprocessing systems; program compilers; program debugging; software tools; system buses; MIMD parallel DSP; PADDI-2; SPARCstation; VGI-1; application development libraries; compilers; custom Sbus controller; debugging tools; graphical SFG tool; hardware configuration; hardware verification; image processing algorithms; image processing system; implementation dependencies; layered encapsulations; multiprocessor DSP system; routing tools; simulator; software environment; software implementations; software tools; Application software; Debugging; Digital signal processing; Digital signal processing chips; Hardware; Image processing; Routing; Software algorithms; Software libraries; Software tools;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1998. Proceedings

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-89791-964-5

Type

conf

Filename

724440