Improved modelling and parameter extraction for parasitic BJT devices in CMOS

Parasitic BJT devices within advanced CMOS processes are regularly used by the circuit designer for increased circuit flexibility. However, these devices have less ideal characteristics than those found in bipolar-only processes and present a challenge for characterisation and parameter extraction. This paper addresses the problem of providing accurate SPICE models for such parasitic devices. The results used in this paper are of a device from a 0.7 μm process. An important obstacle to the accurate determination of Gummel-Poon parameters is the strong correlation between some effects. Frequently, more than one Gummel-Poon parameter contributes to a specific feature of the I-V characteristic such as gain roll-off at high currents. Thus, simple optimisation strategies can give good fits to the measured behaviour but may result in unphysical values for some of the parameters. This paper presents a strategy which enables a full set of DC parameters to be extracted for the Gummel-Poon model in a sequence of steps which operate on well-defined subsets of the data at one time and which reduces the use of optimisation and preserves the physical nature of the parameters. Parameter extraction using reduced dataset and quick-extraction techniques is also discussed in the paper. These techniques are used to provide a large number of parameter sets to be used for statistical analysis. This in-turn allows best-case and worst-case models to be generated for a given process