• DocumentCode
    2085181
  • Title

    CMOS IC fault models, physical defect coverage, and IDDQ testing

  • Author

    Fritzemeier, Ronald R. ; Hawkins, Charles F. ; Soden, Jerry M.

  • Author_Institution
    Sandia Nat. Lab., Albuquerque, NM, USA
  • fYear
    1991
  • fDate
    12-15 May 1991
  • Abstract
    The development of the stuck-at fault (SAF) model is reviewed with emphasis on its relationship to CMOS integrated circuit (IC) technologies. The ability of the SAF model to represent common physical defects in CMOS ICs is evaluated. A test strategy for defect detection, which includes IDDQ testing, is presented
  • Keywords
    CMOS integrated circuits; fault location; integrated circuit testing; CMOS integrated circuit; SAF model; defect detection; fault models; physical defect coverage; physical defects; stuck-at fault; test strategy; CMOS integrated circuits; Circuit faults; Circuit testing; Delay; Electrical fault detection; Fault detection; Integrated circuit modeling; Integrated circuit testing; Logic testing; Semiconductor device modeling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
  • Conference_Location
    San Diego, CA
  • Print_ISBN
    0-7803-0015-7
  • Type

    conf

  • DOI
    10.1109/CICC.1991.164091
  • Filename
    164091
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2085181