800 MB/s DDR NAND Flash Memory Multi-Chip Package With Source-Synchronous Interface for Point-to-Point Ring Topology

Author

Gillingham, Peter ; Chinn, David ; Choi, E. ; Jin-Ki Kim ; Macdonald, Daniel ; Hakjune Oh ; Hong-Beom Pyeon ; Schuetz, Roland

Author_Institution

Conversant Intellectual Property Manage., Inc., Ottawa, ON, Canada

Volume

1

fYear

2013

fDate

2013

Firstpage

811

Lastpage

816

Abstract

A 256 Gb NAND flash memory multi-chip package (MCP) includes eight stacked 32 Gb 2 bit/cell multi-level cell (MLC) die and an 11.6 mm² HyperLink NAND bridge chip providing four internal NAND channels for concurrent memory operations. The bridge chip provides an external 1.2 V unidirectional byte-wide point-to-point source-synchronous double data-rate (DDR) interface for low power 800 MB/s operation in a ring topology. Interface power is reduced by shutting down the phase-locked loop in every second MCP and alternating between edge aligned DDR clock and center aligned DDR clock for source-synchronous data transfer from MCP to MCP.

Keywords

NAND circuits; flash memories; integrated circuit packaging; low-power electronics; multichip modules; phase locked loops; DDR NAND flash memory multichip package; DDR clock; DDR interface; HyperLink NAND bridge chip; MCP; MLC; bit rate 800 Mbit/s; bridge chip; concurrent memory operations; interface power; internal NAND channels; multilevel cell die; phase-locked loop; point-to-point ring topology; source-synchronous data transfer; source-synchronous interface; storage capacity 256 Gbit; storage capacity 32 Gbit; unidirectional byte-wide double data-rate interface; voltage 1.2 V; Disk drives; Flash memeory; High-speed integrated circuits; Integrated circuits; Nonvolatile memory; Disk drives; high speed integrated circuits; nonvolatile memory;

fLanguage

English

Journal_Title

Access, IEEE

Publisher

ieee

ISSN

2169-3536

Type

jour

DOI

10.1109/ACCESS.2013.2294433

Filename

6681893