Title :
Sparse FIR filters and the impact on FPGA area usage
Author :
Patronis, Sean G. ; DeBrunner, Linda S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Florida State Univ., Tallahassee, FL
Abstract :
In FIR filter design, a sparse filter is one that has a majority of zeros for coefficients. Generally, a sparse filter is designed in order to save area and speed up computations, but when implementing a sparse filter in an FPGA the expected area savings may not be realized. This paper shows that sparsity in an FIR filter does not generally translate directly into FPGA space (area) savings on a Virtex-4 FPGA.
Keywords :
FIR filters; field programmable gate arrays; FPGA area usage; field programmable gate arrays; sparse FIR filters; Application specific integrated circuits; Costs; Digital signal processing; Energy consumption; Field programmable gate arrays; Finite impulse response filter; Frequency response; Production; Programmable logic arrays; Transfer functions;
Conference_Titel :
Signals, Systems and Computers, 2008 42nd Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
978-1-4244-2940-0
Electronic_ISBN :
1058-6393
DOI :
10.1109/ACSSC.2008.5074751
