Title :
A 3.3 V, 0.5 μm BiCMOS technology for BiNMOS and ECL gates
Author :
Miyakawa, Hiroyuki ; Norishima, Masayuki ; Niitsu, Youichirou ; Momose, Hiroshi ; Maeguchi, Kenji
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Abstract :
A 0.5-μm BiCMOS technology for achieving speed performance with scaling is described. For the lower supply voltage of 3.3 V, the delay time of the conventional BiCMOS gate becomes almost equal to that of the CMOS gate. A BiNMOS circuit was employed and achieved a speed advantage over the CMOS at 3.3 V. To improve bipolar performance and its ECL (emitter coupled logic) gate delay time, a selectively ion-implanted collector technology, was investigated and a quasi-self-aligned bipolar transistor with double polysilicon layers was utilized. The ECL gave achieved a delay time of 57 ps/stage. Both gates retained the speed performance for the scaling trend
Keywords :
BIMOS integrated circuits; delays; emitter-coupled logic; integrated logic circuits; ion implantation; logic gates; 0.5 micron; 3.3 V; 57 ps; BiCMOS technology; BiNMOS circuit; ECL gates; double polysilicon layers; emitter coupled logic; gate delay time; quasi-self-aligned bipolar transistor; scaling; selectively ion-implanted collector technology; speed performance; Acceleration; Application specific integrated circuits; BiCMOS integrated circuits; CMOS process; CMOS technology; Cutoff frequency; Delay effects; Fabrication; MOSFET circuits; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0015-7
DOI :
10.1109/CICC.1991.164101
