Pitch fragmentation induced odd/even effects in a 36 nm floating gate NAND technology

Author

Beug, M.F. ; Parascandola, S. ; Hoehr, T. ; Müller, T. ; Reichelt, R. ; Müller-Meskamp, L. ; Geiser, P. ; Geppert, T. ; Bach, L. ; Bewersdorff-Sarlette, U. ; Kenny, O. ; Brandl, S. ; Marschner, T. ; Meyer, S. ; Riedel, S. ; Specht, M. ; Manger, D. ; Knöfl

Author_Institution

Qimonda Dresden GmbH & Co. OHG, Dresden, Germany

fYear

2008

fDate

11-14 Nov. 2008

Firstpage

1

Lastpage

5

Abstract

Floating gate NAND flash memory arrays with 64 cells per string and high-k inter poly dielectric have been fabricated on a 36 nm ground rule using sub-lithographic patterning techniques (pitch fragmentation). The influence of pitch fragmentation inherent critical dimension variations on the electrical parameters of the memory cells such as string saturation current, initial threshold voltage, and program/erase performance has been investigated in detail.

Keywords

NAND circuits; flash memories; 36 nm floating gate NAND technology; floating gate NAND flash memory arrays; initial threshold voltage; memory cells; pitch fragmentation; string saturation current; sub-lithographic patterning techniques; Character generation; Costs; High K dielectric materials; High-K gate dielectrics; Lithography; Nonvolatile memory; Plugs; Space technology; Stereolithography; Threshold voltage; Floating gate NAND Flash; double patterning; gate coupling ratio; high-k inter poly dielectric; pitch-fragmentation;

fLanguage

English

Publisher

ieee

Conference_Titel

Non-Volatile Memory Technology Symposium, 2008. NVMTS 2008. 9th Annual

Conference_Location

Pacific Grove, CA

Print_ISBN

978-1-4244-3659-0

Electronic_ISBN

978-1-4244-2411-5

Type

conf

DOI

10.1109/NVMT.2008.4731198

Filename

4731198